Applied Mathematics & Information Sciences

Author Country (or Countries)



SystemC is an emerging standard hardware description language for system-level modeling and design. Formal semantics could give its meaning in a mathematically rigorous and unambiguous way. In this paper, we formalize SystemC both from processes and simulation environment by process algebra, which enables that deduction and verification of the whole simulation procedure are in an integrated and convenient manner. Meanwhile, in order to accommodate event-driven and concurrent properties of SystemC, we adopt event structure characterized by true concurrency, as semantic model of both SystemC and its simulation environment for denotational semantics and operational semantics, as well as demonstrate the correspondence between them. As a result, we propose a unified framework for formalizing SystemC.

Suggested Reviewers