Applied Mathematics & Information Sciences

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The continuously growing functionality of digital video surveillance make the surveillance system integrate more streaming processors for serving more cameras to recoding their raw video streaming data. But the memory subsystem can not provide necessary bandwidth and become the bottleneck of whole system. Therein how to improve the performance of the accessing memory will become a major challenge of designing a modern surveillance system. This study proposes novel memory accessing scheduling algorithms, with a corresponding memory controller, called Self-Adjustable Memory System (SAMS), for a multiple-channel streaming systemon- a-chip. By integrating Access Buffers, Frontend Scheduler, Reorder Block, Backend Scheduler, and two scheduling algorithms, SAMS can provide a sufficient memory bandwidth for the streaming processors with high bandwidth requirements. The utilization of multiple DRAM banks can be improved accordingly. The experimental results illustrate that SAMS will arrange enough bandwidth for the streaming processors that have bursting transferring requirement. The enhanced speedup can achieve 3.9X than conventional memory subsystem.

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