Applied Mathematics & Information Sciences

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Power analysis attacks focus on recovering the secret key of a cryptographic core from measurements of its consumed power when the cryptographic core is in encryption or decryption process. This paper designs a complementary AES decryption algorithm which is implemented in hardware as a complementary counterpart of AES decryption engine to resist power analysis attack. The algorithm which is complementary to AES is denoted as CAES. CAES decryption engine can provide complementary power to AES decryption engine by emulating the ideal of wave dynamic differential logic (WDDL), a power balanced hardware gate style. CAES decryption algorithm is an algorithm level countermeasure which can be easily implemented by hardware description language. This enables designers to design a security IC in a traditional design flow, while WDDL logic circuits employ a customer design flow. This paper specifies the detailed description of the CAES decryption algorithm and its hardware implementation. Correspondingly, we carried out power analysis attacks to AES decryption engines without CAES counterpart and with CAES counterpart. We use very accurate power traces through simulation and FPGA experiment to exhaustively examine our proposed countermeasure. The results show that CAES counterpart can thwart power analysis attacks and it is a promising approach to implement resistant crypto core.

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