Ultra High Voltage Device RESURF LDMOS Technology on Drain- and Source-Centric Design Optimization

Authors

Shao Ming Yang, Department of Computer Science and Information Engineering, AISA University, 41354, TaiwanFollow
Po-An Chen, Nuvoton Corporation, Hsinchu 30077, TaiwanFollow
CH Pan, Nuvoton Corporation, Hsinchu 30077, TaiwanFollow

Author Country (or Countries)

Taiwan

Abstract

We present drain and source-centric design optimizations of a linear P-top and dual-channel conduction path LDMOS (lateral double-diffused metal-oxide semiconductor) structure for low specific on-resistance (Ron.sp) powered transistor devices. The design was simulated using TCAD tools, and a real silicon device was fabricated successfully in accordance with the simulation. The 3D effect in the cylindrical layout with the linear P-top doping profiles was designed using an analytical model to obtain optimal charged balance for the drain- and source-centric regions. The silicon result, with an optimized P-top doping process window, achieved a breakdown voltage (BV) of 842 V, which was higher than 800 V. Thus, the use of a dual-channel conduction path technique with an N-top layer implanted over the P-top can improve Ron.sp by 25% without compromising BV.

Digital Object Identifier (DOI)

http://dx.doi.org/10.18576/amis/100620

Recommended Citation

Ming Yang, Shao; Chen, Po-An; and Pan, CH (2016) "Ultra High Voltage Device RESURF LDMOS Technology on Drain- and Source-Centric Design Optimization," Applied Mathematics & Information Sciences: Vol. 10: Iss. 6, Article 20.
DOI: http://dx.doi.org/10.18576/amis/100620
Available at: https://digitalcommons.aaru.edu.jo/amis/vol10/iss6/20