Efficient String Matching FPGA for speed up Network Intrusion Detection

Authors

J. Armstrong Joseph, Dept. of ICE, Anna University, Chennai, India.Follow
Reeba Korah, Alliance College of Engineering and Design, Alliance University, Bangaluru, IndiaFollow
S. Salivahanan, SSN College of Engineering, Chennai, India.Follow

Author Country (or Countries)

India.

Abstract

Malicious attacks and threats over network can be identified and prevented by Intrusion detection system (IDS). Essential ability of every intrusion detection system is to search and find packet content that can matches distinguished attacks. An open source Network Intrusion Detection System (NIDS) is Snort that utilizes signatures/rules for detecting irregular network activities. Softwarebased IDSmay not be continued to process all traffic in real-time when network traffic increased. On the other hand, hardware based IDS are best suited for computing and serious processing on network traffic and can keep up high network throughput. This paper, contributes Buffered Boyer-Moore string-matching algorithm using FPGA that drastically increase throughput and improve its performance on hardware implementations. The projected performance as Performance Efficiency Metric (PEM) 21.3 enables system to do 19.2 Gbps of throughput and implies a significant difference obtained when processing large number of payload.

Digital Object Identifier (DOI)

http://dx.doi.org/10.18576/journal/100314

Recommended Citation

Armstrong Joseph, J.; Korah, Reeba; and Salivahanan, S. (2018) "Efficient String Matching FPGA for speed up Network Intrusion Detection," Applied Mathematics & Information Sciences: Vol. 12: Iss. 2, Article 14.
DOI: http://dx.doi.org/10.18576/journal/100314
Available at: https://digitalcommons.aaru.edu.jo/amis/vol12/iss2/14