In this paper, a new low power, high speed network multiplier is presented. For increasing performance of multiplier, a novel modified high-order encoder is proposed. Previous encoders have complicated hardware and their ability to decrease number of input operands is low. Presented encoder uses high-order algorithm and therefore reduces number of partial products efficiently. A new hybrid adder is presented which uses ideas of carry lookahead adder and ripple carry adder to modify final adder architecture. Previous carry lookahead adders have large carry network and their ability to decrease noise margin is low. It uses a DCVS carry network, which provides high speed and less wiring problems in compare with previous algorithms. Proposed hybrid adder has major effect on multiplier efficiency. A new network array is presented which uses high performance modules. Using a new algorithm, this study reduces critical path of tree multiplier. A novel counter is implemented which uses less transistor count and less power consumption in compare with previous algorithms. This counter uses pass transistor technology. Transistor connections, in mentioned counter are implemented in a new efficient way. The new multiplier has better efficiency in different electronic and algorithmic parameters in compare with previous implementations.
"A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology,"
Information Sciences Letters: Vol. 2
, Article 5.
Available at: https://digitalcommons.aaru.edu.jo/isl/vol2/iss3/5