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Effat Undergraduate Research Journal

Abstract

The radio spectrum, an inherently limited resource, has been increasingly utilized owing to the recent exponential growth of wireless services. This has led to a new approach, termed cognitive radio, predicated upon exploitation of spectrum holes for omnipresent spectrum utilization. This is made possible via cognitive radio networks’ employment of spectrum sensing. Wideband spectrum sensing has been the focal challenge point in cognitive radio technology, since existing techniques are reliant on analog to digital converters (ADC) with sampling at the Nyquist rate. Unfortunately, in order to perform digitization of wideband RF signals at the Nyquist rate, a very high sampling frequency is required with primarily complex and energy inefficient designs. In this paper, a wideband spectrum sensing design is proposed utilizing Compressive Sensing, which enables sampling far below the Nyquist rate and thus drastically reduces power consumption, complexity and cost of the system. The proposed design is an 8-bit Under-sampled Successive Approximation Register (SAR) ADC. The core blocks of an SAR ADC design are the SAR Logic Block and the comparator, both of which were designed and simulated in Cadence software. The design was implemented in targeted technology of 65 nm standard CMOS technology. An optimization method suitable for VLSI implementation, termed Orthogonal Matching Pursuit (OMP), was utilized for spectrum recovery. Following comparative analyses with previously published studies, we demonstrate significant improvements in terms of speed and chip area of the SAR ADC design proposed herein.

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